1. Field of the Invention
The present invention relates to a magnetic random access memory (MRAM), which incorporates tunnel magnetoresistive elements within memory cells.
2. Description of the Related Art
In an MRAM memory cell, the resistance of a magnetic tunnel junction represents the cell data. In a commonly-known method for reading cell data from a memory cell of an MRAM, a predetermined voltage is applied to the memory cell, and the cell data is identified from the current through the memory cell, as disclosed in Japanese Laid-Open Patent Applications Nos. JP-A 2004-206796 and JP-A 2004-213771. Additionally, Japanese Laid-Open Patent Application No. JP-A 2005-182986 discloses a memory device incorporating cross-point resistor elements in which cell data is identified from the current through the associated cross-point resistor element. However, these conventional methods suffer from problems that current-voltage conversion, which takes considerable time, is required, and that the size of the read circuitry is undesirably increased.
One approach for solving these problems is to identify cell data from a voltage generated across an MRAM memory cell, as disclosed in Japanese Laid-Open Patent Application No. JP-A 2004-220759. FIG. 1 illustrates an equivalent circuit diagram of a memory cell disclosed in this patent application. The memory cell is composed of a pair of magnetoresistive elements each incorporating an MTJ, and a pair of transistors MN101 and MN102. In FIG. 2, the magnetoresistive elements J100 and J101 are represented as variable resistors.
In the memory cell shown in FIG. 1, complementary data are written into the magnetoresistive elements J100 and J101, which are connected in serial. The data write is achieved by generating write currents Iwx, Iwy0 and Iwy1 through a write word line WWL, a pair of write bitlines WBL and /WBL, respectively. The write currents Iwx, Iwy0 and Iwy1 generate a magnetic field to thereby write complementary data into the magnetoresistive elements 1100 and J101. When the high resistance state corresponds to a data “1” and the low resistance state corresponds to a data “0”, the magnetoresistive elements J100 and J101 are written with data “0” and “1”, respectively, or with data “1” and “0”, respectively.
The data read is achieved by activating a read word line RWL, and driving the write bitlines WBL and /WBL to the power source voltage level (Vdd) and the ground voltage level (Vss), respectively. The generation of a voltage of Vdd-Vss between the write bitlines WBL and /WBL causes a read current Ir to flow through the magnetoresistive elements J100 and J101, and this generates a voltage level corresponding to the data written into the magnetoresistive elements J100 and J101 on a read bitline RBL.
One advantage of this memory cell architecture is that the output signal of the memory cell is a voltage signal and therefore the output signal can be rapidly amplified by a sense amplifier circuit, as is the case of the conventional DRAM memory cell architecture.
Japanese Laid-open Patent Application No. JP-A 2002-269968 discloses Another MRAM that identifies cell data from a voltage generated across an MRAM memory cell.
The selection of a memory cell to be written with write data in an MRAM is often achieved by using a transistor or a diode. Such a memory cell is disclosed in Japanese Laid-Open Patent Application No. JP-A 2004-348934. FIG. 2 is an equivalent circuit diagram of the disclosed memory cell. The MRAM memory cell shown in FIG. 2 is composed of a magnetoresistive element J102 and a pair of NMOS transistors MN102 and MN103. In the memory cell shown in FIG. 2, the write current is generated only through a memory cell desired to be written with write data, and the data write is achieved by the write current generated through the desired memory cell. More specifically, the data write is achieved by generating a current flowing from the bitline BL to the bitline /BL with the word line WL activated. This method effectively improves the selectivity of memory cells in write operations.
One problem of an MRAM which identifies cell data from the voltage generated across the memory cell is that the signal level obtained from the memory cell is not so large. The small signal level obtained from the memory cell makes it difficult to identify cell data, and undesirably hinders the improvement of the data read speed.